The present invention relates to techniques for semiconductor integrated circuit design process, and more particularly relates to design of a semiconductor integrated circuit having air gaps formed therein, support of the design of the semiconductor integrated circuit, and calculation of wiring parasitic capacitance in the design process of the semiconductor integrated circuit.
As miniaturization of semiconductor fabrication processes has been advanced, the spacing between signal wires in a semiconductor integrated circuit has been narrowed to increase the resulting wiring parasitic capacitance between the signal wires. As a result, the adverse effects of wiring delay and cross talk noise, which cause the design period to be extended and the performance to be degraded, can no longer be ignored.
In order to reduce the wiring parasitic capacitance between signal wires, there has been an air gap producing technique, in which air gaps are formed between the signal wires. In the “air gap” structure, air gaps are formed in an insulating film between wires. This structure allows the insulating film to have a lower dielectric constant than conventional ones, thereby enabling the wiring parasitic capacitance between the signal wires to be reduced.
Such air gap producing methods were disclosed in Japanese Examined Patent Application Publication No. 7-114236 (Patent Document 1) and in Japanese Laid-Open Publication No. 7-326670 (Patent Document 2). In the methods disclosed in these patent documents, a CVD process or a sputtering process are used to form air gaps in part of an insulating film between wires in a semiconductor integrated circuit. The part where the air gaps are formed and the volume of the air gaps are limited by the space between the wires. Specifically, if the space between wires is large, no air gaps can be formed therebetween. Also, Japanese Patent No. 348122 (Patent Document 3) proposed a technique for creating air gaps by controlling the spacing between wires.
To reduce the wiring parasitic capacitance between wires in a semiconductor integrated circuit, it is desired that many air gaps be created. However, if too many air gaps are present in a semiconductor integrated circuit, resistance to thermal and mechanical stresses may decrease, and if the locations and volumes of created air gaps are uneven in the chip, irregularities may occur in the chip.
In designing a miniaturized large-scale semiconductor integrated circuit, the designing must be performed in such a manner that various kinds of constraints not only as to air gaps but also as to delay, area, fabrication rules, etc. are satisfied. These constraints must be taken into account throughout the entire design process of the semiconductor integrated circuit. The constraints on air gaps thus also have to be considered throughout the entire design process of the semiconductor integrated circuit.
Nevertheless, the disclosed methods only show how to create air gaps in the fabrication process of a semiconductor integrated circuit, and no designing methods have been disclosed in which air gap formation is taken into account in the design process (such as a logic synthesis process and a layout process) of a semiconductor integrated circuit.